Datasheet

Chapter 3 Port Integration Module (PIM9E128V1)

MC9S12E128 Data Sheet, Rev. 1.07

164 Freescale Semiconductor

Figure 3-52. Pulse Illustration

A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4

consecutive samples of an active level directly or indirectly

The filters are continuously clocked by the bus clock in RUN and WAIT mode. In STOP mode the clock

is generated by a single RC oscillator in the port integration module. To maximize current saving the RC

oscillator runs only if the following condition is true on any pin:

Sample count <= 4 and port interrupt enabled (PIE=1) and port interrupt flag not set (PIF=0).

3.6.2 Interrupt Sources

NOTE

Vector addresses and their relative interrupt priority are determined at the

MCU level.

3.6.3 Operation in Stop Mode

All clocks are stopped in STOP mode. The port integration module has asynchronous paths on port AD to

generate wake-up interrupts from stop mode. For other sources of external interrupts refer to the respective

block description chapters.

Table 3-39. Port Integration Module Interrupt Sources

Interrupt

Source

Interrupt

Flag

Local

Enable

Global (CCR)

Mask

Port AD PIFAD[15:0] PIEAD[15:0] I Bit

pulse