Datasheet

Chapter 4 Clocks and Reset Generator (CRGV4)
MC9S12E128 Data Sheet, Rev. 1.07
168 Freescale Semiconductor
Figure 4-2. PLL Loop Filter Connections
4.2.3 RESET — Reset Pin
RESET is an active low bidirectional reset pin. As an input it initializes the MCU asynchronously to a
known start-up state. As an open-drain output it indicates that an system reset (internal to MCU) has been
triggered.
4.3 Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the CRGV4.
4.3.1 Module Memory Map
Table 4-1 gives an overview on all CRGV4 registers.
Table 4-1. CRGV4 Memory Map
Address
Offset
Use Access
0x0000 CRG Synthesizer Register (SYNR) R/W
0x0001 CRG Reference Divider Register (REFDV) R/W
0x0002 CRG Test Flags Register (CTFLG)
1
1
CTFLG is intended for factory test purposes only.
R/W
0x0003 CRG Flags Register (CRGFLG) R/W
0x0004 CRG Interrupt Enable Register (CRGINT) R/W
0x0005 CRG Clock Select Register (CLKSEL) R/W
0x0006 CRG PLL Control Register (PLLCTL) R/W
0x0007 CRG RTI Control Register (RTICTL) R/W
0x0008 CRG COP Control Register (COPCTL) R/W
0x0009 CRG Force and Bypass Test Register (FORBYP)
2
2
FORBYP is intended for factory test purposes only.
R/W
0x000A CRG Test Control Register (CTCTL)
3
3
CTCTL is intended for factory test purposes only.
R/W
0x000B CRG COP Arm/Timer Reset (ARMCOP) R/W
MCU
XFC
RS
CS
V
DDPLL
CP