Datasheet

Chapter 4 Clocks and Reset Generator (CRGV4)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 169
NOTE
Register address = base address + address offset, where the base address is
defined at the MCU level and the address offset is defined at the module
level.
4.3.2 Register Descriptions
This section describes in address order all the CRGV4 registers and their individual bits.
Register
Name
Bit 7 654321Bit 0
SYNR R 0 0
SYN5 SYN4 SYN3 SYN2 SYN1 SYN0
W
REFDV R 0000
REFDV3 REFDV2 REFDV1 REFDV0
W
CTFLG R 00000000
W
CRGFLG R
RTIF PORF LVRF LOCKIF
LOCK TRACK
SCMIF
SCM
W
CRGINT R
RTIE
00
LOCKIE
00
SCMIE
0
W
CLKSEL R
PLLSEL PSTP SYSWAI ROAWAI PLLWAI CWAI RTIWAI COPWAI
W
PLLCTL R
CME PLLON AUTO ACQ
0
PRE PCE SCME
W
RTICTL R 0
RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0
W
COPCTL R
WCOP RSBCK
000
CR2 CR1 CR0
W
FORBYP R 00000000
W
CTCTL R 00000000
W
= Unimplemented or Reserved
Figure 4-3. CRG Register Summary