Datasheet

Chapter 4 Clocks and Reset Generator (CRGV4)
MC9S12E128 Data Sheet, Rev. 1.07
170 Freescale Semiconductor
4.3.2.1 CRG Synthesizer Register (SYNR)
The SYNR register controls the multiplication factor of the PLL. If the PLL is on, the count in the loop
divider (SYNR) register effectively multiplies up the PLL clock (PLLCLK) from the reference frequency
by 2 x (SYNR+1). PLLCLK will not be below the minimum VCO frequency (f
SCM
).
NOTE
If PLL is selected (PLLSEL=1), Bus Clock = PLLCLK / 2
Bus Clock must not exceed the maximum operating system frequency.
Read: anytime
Write: anytime except if PLLSEL = 1
NOTE
Write to this register initializes the lock detector bit and the track detector
bit.
ARMCOP R 00000000
W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
76543210
R0 0
SYN5 SYNR SYN3 SYN2 SYN1 SYN0
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 4-4. CRG Synthesizer Register (SYNR)
Register
Name
Bit 7 654321Bit 0
= Unimplemented or Reserved
Figure 4-3. CRG Register Summary (continued)
PLLCLK 2xOSCCLKx
SYNR 1+()
REFDV 1+()
-----------------------------------
=