Datasheet
Chapter 4 Clocks and Reset Generator (CRGV4)
MC9S12E128 Data Sheet, Rev. 1.07
172 Freescale Semiconductor
4.3.2.4 CRG Flags Register (CRGFLG)
This register provides CRG status bits and flags.
Read: anytime
Write: refer to each bit for individual write conditions
76543210
R
RTIF PORF LVRF LOCKIF
LOCK TRACK
SCMIF
SCM
W
Reset 0 Note 1 Note 2 00000
1. PORF is set to 1 when a power-on reset occurs. Unaffected by system reset.
2. LVRF is set to 1 when a low-voltage reset occurs. Unaffected by system reset.
= Unimplemented or Reserved
Figure 4-7. CRG Flag Register (CRGFLG)
Table 4-2. CRGFLG Field Descriptions
Field Description
7
RTIF
Real-Time Interrupt Flag — RTIF is set to 1 at the end of the RTI period. This flag can only be cleared by writing
a 1. Writing a 0 has no effect. If enabled (RTIE = 1), RTIF causes an interrupt request.
0 RTI time-out has not yet occurred.
1 RTI time-out has occurred.
6
PORF
Power-on Reset Flag — PORF is set to 1 when a power-on reset occurs. This flag can only be cleared by writing
a 1. Writing a 0 has no effect.
0 Power-on reset has not occurred.
1 Power-on reset has occurred.
5
LVRF
Low-Voltage Reset Flag — If low voltage reset feature is not available (see the device overview chapter), LVRF
always reads 0. LVRF is set to 1 when a low voltage reset occurs. This flag can only be cleared by writing a 1.
Writing a 0 has no effect.
0 Low voltage reset has not occurred.
1 Low voltage reset has occurred.
4
LOCKIF
PLL Lock Interrupt Flag — LOCKIF is set to 1 when LOCK status bit changes. This flag can only be cleared by
writing a 1. Writing a 0 has no effect.If enabled (LOCKIE = 1), LOCKIF causes an interrupt request.
0 No change in LOCK bit.
1 LOCK bit has changed.
3
LOCK
Lock Status Bit — LOCK reflects the current state of PLL lock condition. This bit is cleared in self-clock mode.
Writes have no effect.
0 PLL VCO is not within the desired tolerance of the target frequency.
1 PLL VCO is within the desired tolerance of the target frequency.
2
TRACK
Track Status Bit — TRACK reflects the current state of PLL track condition. This bit is cleared in self-clock mode.
Writes have no effect.
0 Acquisition mode status.
1 Tracking mode status.