Datasheet

Chapter 4 Clocks and Reset Generator (CRGV4)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 173
4.3.2.5 CRG Interrupt Enable Register (CRGINT)
This register enables CRG interrupt requests.
Read: anytime
Write: anytime
1
SCMIF
Self-Clock Mode Interrupt Flag — SCMIF is set to 1 when SCM status bit changes. This flag can only be
cleared by writing a 1. Writing a 0 has no effect. If enabled (SCMIE=1), SCMIF causes an interrupt request.
0 No change in SCM bit.
1 SCM bit has changed.
0
SCM
Self-Clock Mode Status Bit — SCM reflects the current clocking mode. Writes have no effect.
0 MCU is operating normally with OSCCLK available.
1 MCU is operating in self-clock mode with OSCCLK in an unknown state. All clocks are derived from PLLCLK
running at its minimum frequency f
SCM
.
76543210
R
RTIE
00
LOCKIE
00
SCMIE
0
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 4-8. CRG Interrupt Enable Register (CRGINT)
Table 4-3. CRGINT Field Descriptions
Field Description
7
RTIE
Real-Time Interrupt Enable Bit
0 Interrupt requests from RTI are disabled.
1 Interrupt will be requested whenever RTIF is set.
4
LOCKIE
Lock Interrupt Enable Bit
0 LOCK interrupt requests are disabled.
1 Interrupt will be requested whenever LOCKIF is set.
1
SCMIE
Self-Clock Mode Interrupt Enable Bit
0 SCM interrupt requests are disabled.
1 Interrupt will be requested whenever SCMIF is set.
Table 4-2. CRGFLG Field Descriptions (continued)
Field Description