Datasheet

Chapter 4 Clocks and Reset Generator (CRGV4)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 185
Figure 4-19. Check Window Example
The sequence for clock quality check is shown in Figure 4-20.
Figure 4-20. Sequence for Clock Quality Check
NOTE
Remember that in parallel to additional actions caused by self-clock mode
or clock monitor reset
1
handling the clock quality checker continues to
check the OSCCLK signal.
1. A Clock Monitor Reset will always set the SCME bit to logical’1’
12
49999
50000
VCO
clock
check window
12345
4095
4096
3
OSCCLK
osc ok
check window
osc ok
?
SCM
active?
Switch to OSCCLK
Exit SCM
Clock OK
num=0
num<50
?
num=num+1
yes
no
yes
SCME=1
?
no
Enter SCM
SCM
active?
yes
Clock Monitor Reset
no
yes
no
num=50
yes
no
POR exit full stop
CM fail
LVR