Datasheet

Chapter 4 Clocks and Reset Generator (CRGV4)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 187
4.4.6 Real-Time Interrupt (RTI)
The RTI can be used to generate a hardware interrupt at a fixed periodic rate. If enabled (by setting
RTIE=1), this interrupt will occur at the rate selected by the RTICTL register. The RTI runs with a gated
OSCCLK (see Section Figure 4-22., “Clock Chain for RTI”). At the end of the RTI time-out period the
RTIF flag is set to 1 and a new RTI time-out period starts immediately.
A write to the RTICTL register restarts the RTI time-out period.
If the PRE bit is set, the RTI will continue to run in pseudo-stop mode.
.
Figure 4-22. Clock Chain for RTI
4.4.7 Modes of Operation
4.4.7.1 Normal Mode
The CRGV4 block behaves as described within this specification in all normal modes.
4.4.7.2 Self-Clock Mode
The VCO has a minimum operating frequency, f
SCM
. If the external clock frequency is not available due
to a failure or due to long crystal start-up time, the bus clock and the core clock are derived from the VCO
OSCCLK
RTR[6:4]
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
COUNTER (RTR[3:0])
4-BIT MODULUS
÷ 1024
RTI TIMEOUT
= Clock Gate
WAIT(RTIWAI),
STOP(PSTP,PRE),
RTI enable
gating condition