Datasheet

Chapter 4 Clocks and Reset Generator (CRGV4)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 189
Figure 4-23. Wait Mode Entry/Exit Sequence
Enter
Wait Mode
PLLWAI=1
?
Exit Wait w.
CMRESET
Exit Wait w.
ext.RESET
Exit
Wait Mode
Enter
SCM
Exit
Wait Mode
Core req’s
Wait Mode.
CWAI or
SYSWAI=1
?
SYSWAI=1
?
Clear
PLLSEL,
Disable PLL
Disable
core clocks
Disable
system clocks
CME=1
?
INT
?
CM fail
?
SCME=1
?
SCMIE=1
?
Continue w.
normal OP
no
no
no
no
no
no
no
yes
yes
yes
yes
yes
no
yes
yes
yes
Wait Mode left
due to external
reset
Generate
SCM Interrupt
(Wakeup from Wait)
SCM=1
?
Enter
SCM
no
yes