Datasheet

Chapter 6 Analog-to-Digital Converter (ATD10B16CV2)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 211
Read: always read $00 in normal modes
Write: unimplemented in normal modes
6.3.2.3 ATD Control Register 2 (ATDCTL2)
This register controls power down, interrupt and external trigger. Writes to this register will abort current
conversion sequence but will not start a new sequence.
Read: Anytime
Write: Anytime
76543210
R
ADPU AFFC AWAI ETRIGLE ETRIGP ETRIGE ASCIE
ASCIF
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 6-5. ATD Control Register 2 (ATDCTL2)
Table 6-2. ATDCTL2 Field Descriptions
Field Description
7
ADPU
ATD Power Down — This bit provides on/off control over the ATD10B16C block allowing reduced MCU power
consumption. Because analog electronic is turned off when powered down, the ATD requires a recovery time
period after ADPU bit is enabled.
0 Power down ATD
1 Normal ATD functionality
6
AFFC
ATD Fast Flag Clear All
0 ATD flag clearing operates normally (read the status register ATDSTAT1 before reading the result register
to clear the associate CCF flag).
1 Changes all ATD conversion complete flags to a fast clear sequence. Any access to a result register will
cause the associate CCF flag to clear automatically.
5
AWAI
ATD Power Down in Wait Mode — When entering Wait Mode this bit provides on/off control over the
ATD10B16C block allowing reduced MCU power. Because analog electronic is turned off when powered down,
the ATD requires a recovery time period after exit from Wait mode.
0 ATD continues to run in Wait mode
1 Halt conversion and power down ATD during Wait mode
After exiting Wait mode with an interrupt conversion will resume. But due to the recovery time the result of
this conversion should be ignored.
4
ETRIGLE
External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See
Table 6-3 for details.
3
ETRIGP
External Trigger Polarity — This bit controls the polarity of the external trigger signal. See Table 6-3 for
details.
2
ETRIGE
External Trigger Mode Enable — This bit enables the external trigger on ATD channel 15. The external trigger
allows to synchronize the start of conversion with external events.
0 Disable external trigger
1 Enable external trigger