Datasheet

Chapter 7 Digital-to-Analog Converter (DAC8B1CV1)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 241
7.3.2.2 Reserved Register (DACC1)
This register is reserved.
Read: always read $00
Write: unimplemented
7.3.2.3 DAC Data Register — Left Justified (DACD)
Read: read zeroes when DJM is set
Write: unimplemented when DJM is set
The DAC data register is an 8-bit readable/writable register that stores the data to be converted when DJM
bit is clear. When the DACE bit is set, the value in this register is converted into an analog voltage such
that values from $00 to $FF result in equal voltage increments from V
SSA
to V
REF
. When DJM bit is set,
this register reads zeroes and cannot be written.
Module Base + 0x0000
76543210
R00000000
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 7-4. Reserved Register (DACC1)
Module Base + 0x0002
76543210
R
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
W
Reset 0 0 0 00000
Figure 7-5. DAC Data Register — Left Justified (DACD)