Datasheet

Chapter 8 Serial Communication Interface (SCIV3)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 261
8.4.3 Baud Rate Generation
A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the
transmitter. The value from 0 to 8191 written to the SBR[12:0] bits determines the module clock divisor.
The SBR bits are in the SCI baud rate registers (SCIBDH and SCIBDL). The baud rate clock is
synchronized with the bus clock and drives the receiver. The baud rate clock divided by 16 drives the
transmitter. The receiver has an acquisition rate of 16 samples per bit time.
Baud rate generation is subject to one source of error:
• Integer division of the module clock may not give the exact target frequency.
Table 8-13 lists some examples of achieving target baud rates with a module clock frequency of 10.2 MHz.
When IREN = 0 then,
SCI baud rate = SCI module clock / (16 * SCIBR[12:0])
Table 8-13. Baud Rates (Example: Module Clock = 10.2 MHz)
Bits
SBR[12–0]
Receiver
Clock (Hz)
Transmitter
Clock (Hz)
Target Baud
Rate
Error
(%)
17 600,000.0 37,500.0 38,400 2.3
33 309,090.9 19,318.2 19,200 .62
66 154,545.5 9659.1 9600 .62
133 76,691.7 4793.2 4800 .14
266 38,345.9 2396.6 2400 .14
531 19,209.0 1200.6 1200 .11
1062 9604.5 600.3 600 .05
2125 4800.0 300.0 300 .00
4250 2400.0 150.0 150 .00
5795 1760.1 110.0 110 .00