Datasheet

Chapter 8 Serial Communication Interface (SCIV3)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 265
TDRE flag is set and immediately before writing the next byte to the SCI
data register.
If the TE bit is clear and the transmission is complete, the SCI is not the
master of the TXD pin
8.4.5 Receiver
Figure 8-14. SCI Receiver Block Diagram
8.4.5.1 Receiver Character Length
The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI
control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in
SCI data register high (SCIDRH) is the ninth bit (bit 8).
8.4.5.2 Character Reception
During an SCI reception, the receive shift register shifts a frame in from the RXD pin. The SCI data
register is the read-only buffer between the internal data bus and the receive shift register.
After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the
SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCISR1) becomes set,
ALL ONES
M
WAKE
ILT
PE
PT
RE
H876543210L
11-BIT RECEIVE SHIFT REGISTER STOP START
DATA
WAKEUP
PARITY
CHECKING
MSB
SCI DATA REGISTER
R8
RIE
ILIE
RWU
RDRF
OR
NF
FE
PE
INTERNAL BUS
BUS
IDLE INTERRUPT REQUEST
RDRF/OR INTERRUPT REQUEST
SBR12–SBR0
BAUD
CLOCK
IDLE
RAF
RECOVERY
LOGIC
LOOPS
LOOP
RSRC
CONTROL
SCRXD
FROM TXD PIN
OR TRANSMITTER
DIVIDER