Datasheet

Chapter 8 Serial Communication Interface (SCIV3)
MC9S12E128 Data Sheet, Rev. 1.07
266 Freescale Semiconductor
indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in SCI control register
2 (SCICR2) is also set, the RDRF flag generates an RDRF interrupt request.
8.4.5.3 Data Sampling
The receiver samples the RXD pin at the RT clock rate. The RT clock is an internal signal with a frequency
16 times the baud rate. To adjust for baud rate mismatch, the RT clock (see Figure 8-15) is
re-synchronized:
• After every start bit
• After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit
samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three
logic 1s. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
Figure 8-15. Receiver Data Sampling
To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7.
Table 8-14 summarizes the results of the start bit verification samples.
If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins.
Table 8-14. Start Bit Verification
RT3, RT5, and RT7 Samples Start Bit Verification Noise Flag
000 Yes 0
001 Yes 1
010 Yes 1
011 No 0
100 Yes 1
101 No 0
110 No 0
111 No 0
RESET RT CLOCK
RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT8 RT7 RT6
RT11 RT10
RT9
RT15 RT14 RT13 RT12 RT16
RT1 RT2 RT3 RT4
SAMPLES
RT CLOCK
RT CLOCK COUNT
START BIT
RXD
START BIT
QUALIFICATION
START BIT DATA
SAMPLING
111111110000000
LSB
VERIFICATION