Datasheet

Chapter 9 Serial Peripheral Interface (SPIV3)
MC9S12E128 Data Sheet, Rev. 1.07
278 Freescale Semiconductor
9.1.3 Block Diagram
Figure 9-1 gives an overview on the SPI architecture. The main parts of the SPI are status, control, and data
registers, shifter logic, baud rate generator, master/slave control logic, and port control logic.
Figure 9-1. SPI Block Diagram
9.2 External Signal Description
This section lists the name and description of all ports including inputs and outputs that do, or may, connect
off chip. The SPIV3 module has a total of four external pins.
9.2.1 MOSI — Master Out/Slave In Pin
This pin is used to transmit data out of the SPI module when it is configured as a master and receive data
when it is configured as slave.
SPI Control Register 1
SPI Control Register 2
SPI Baud Rate Register
SPI Status Register
SPI Data Register
Shifter
Port
Control
Logic
MOSI
SCK
Interrupt Control
SPI
MSB
LSB
LSBFE=1 LSBFE=0
LSBFE=0 LSBFE=1
data in
LSBFE=1
LSBFE=0
data out
8
8
Baud Rate Generator
Prescaler
Bus Clock
Counter
Clock Select
SPPR
3
3
SPR
Baud Rate
Phase +
Polarity
Control
Master
Slave
SCK in
SCK out
Master Baud Rate
Slave Baud Rate
Phase +
Polarity
Control
Control
Control
CPOL
CPHA
2
BIDIROE
SPC0
2
MODFSPIF SPTEF
SPI
Request
Interrupt
SS
Shift
Clock
Sample
Clock