Datasheet

Chapter 10 Inter-Integrated Circuit (IICV2)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 321
Figure 10-11. Flow-Chart of Typical IIC Interrupt Routine
Clear
Master
Mode
?
Tx/Rx
?
Last Byte
Transmitted
?
RXAK=0
?
End Of
Addr Cycle
(Master Rx)
?
Write Next
Byte To IBDR
Switch To
Rx Mode
Dummy Read
From IBDR
Generate
Stop Signal
Read Data
From IBDR
And Store
Set TXAK =1
Generate
Stop Signal
2nd Last
Byte To Be Read
?
Last
Byte To Be Read
?
Arbitration
Lost
?
Clear IBAL
IAAS=1
?
IAAS=1
?
SRW=1
?
TX/RX
?
Set TX
Mode
Write Data
To IBDR
Set RX
Mode
Dummy Read
From IBDR
ACK From
Receiver
?
Tx Next
Byte
Read Data
From IBDR
And Store
Switch To
Rx Mode
Dummy Read
From IBDR
RTI
YN
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
Y
TX RX
RX
TX
(Write)
(Read)
N
IBIF
Address Transfer
Data Transfer