Datasheet

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 335
11.3.2.5 PMF Fault Control Register (PMFFCTL)
Read and write anytime.
11.3.2.6 PMF Fault Pin Enable Register (PMFFPIN)
Read anytime. This register cannot be modified after the WP bit is set.
Module Base + 0x0004
76543210
R
FMODE3 FIE3 FMODE2 FIE2 FMODE1 FIE1 FMODE0 FIE0
W
Reset 0 0 0 00000
Figure 11-8. PMF Fault Control Register (PMFFCTL))
Table 11-6. PMFFCTL Field Descriptions
Field Description
7, 5, 3, 1
FMODE[3:0]
Fault x Pin Clearing Mode — This bit selects automatic or manual clearing of FAULTx pin faults. See
Section 11.4.8.2, “Automatic Fault Clearing” and Section 11.4.8.3, “Manual Fault Clearing” for more details.
0 Manual fault clearing of FAULTx pin faults.
1 Automatic fault clearing of FAULTx pin faults.
where x is 0, 1, 2, and 3.
6, 4, 2, 0
FIE[3:0]
Fault x Pin Interrupt Enable — This bit enables CPU interrupt requests to be generated by the FAULTx pin. The
fault protection circuit is independent of the FIEx bit and is active when FPINEx is set. If a fault is detected, the
PWM pins are disabled according to the PMF Disable Mapping registers.
0 Fault x CPU interrupt requests disabled.
1 Fault x CPU interrupt requests enabled.
where x is 0, 1, 2 and 3.
Module Base + 0x0005
76543210
R0
FPINE3
0
FPINE2
0
FPINE1
0
FPINE0
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 11-9. PMF Fault Pin Enable Register (PMFFPIN)
Table 11-7. PMFFPIN Field Descriptions
Field Description
6, 4, 2, 0
FPINE[2:0]
Fault x Pin Enable — Where x is 0, 1, 2 and 3.
0 FAULTx pin is disabled for fault protection.
1 FAULTx pin is enabled for fault protection.