Datasheet

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
MC9S12E128 Data Sheet, Rev. 1.07
340 Freescale Semiconductor
11.3.2.12 PMF Deadtime Sample Register (PMFDTMS)
Read anytime and writes have no effect.
11.3.2.13 PMF Correction Control Register (PMFCCTL)
Read and write anytime.
Module Base + 0x000E
76543210
R 0 0 DT5 DT4 DT3 DT2 DT1 DT0
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 11-18. PMF Deadtime Sample Register (PMFDTMS))
Table 11-16. PMFDTMS Field Descriptions
Field Description
5–0
DT[5:0]
PMF Deadtime Sample Bits — The DTx bits are grouped in pairs, DT0 and DT1, DT2 and DT3, DT4, and DT5.
Each pair reflects the corresponding
ISx pin value as sampled at the end of deadtime.
Module Base + 0x000F
76543210
R0 0
ISENS
0
IPOLC IPOLB IPOLA
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 11-19. PMF Correction Control Register (PMFCCTL)
Table 11-17. PMFCCTL Field Descriptions
Field Description
5–4
ISENS
Current Status Sensing Method — This field selects the top/bottom correction scheme, illustrated in
Table 11-18.
Note: Assume the user will provide current sensing circuitry causing the voltage at the corresponding input pin
to be low for positive current and high for negative current. In addition, it assumes the top PWMs are PWM
0, 2, and 4 while the bottom PWMs are PWM 1, 3, and 5.
Note: The ISENS bits are not buffered. Changing the current status sensing method can affect the present PWM
cycle.