Datasheet

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 341
Table 11-18. Correction Method Selection
2
IPOLC
Current Polarity — This buffered bit selects the PMF Value register for the PWM4 and PWM5 pins in top/bottom
software correction in complementary mode.
0 PMF Value 4 register in next PWM cycle.
1 PMF Value 5 register in next PWM cycle.
Note: The IPOLx bits take effect at the beginning of the next load cycle, regardless of the state of the load okay
bit, LDOK. Select top/bottom software correction by writing 01 to the current select bits, ISENS[1:0], in the
PWM control register. Reading the IPOLx bits read the buffered value and not necessarily the value
currently in effect.
1
IPOLB
Current Polarity — This buffered bit selects the PMF Value register for the PWM2 and PWM3 pins in top/bottom
software correction in complementary mode.
0 PMF Value 2 register in next PWM cycle.
1 PMF Value 3 register in next PWM cycle.
Note: The IPOLx bits take effect at the beginning of the next load cycle, regardless of the state of the load okay
bit, LDOK. Select top/bottom software correction by writing 01 to the current select bits, ISENS[1:0], in the
PWM control register. Reading the IPOLx bits read the buffered value and not necessarily the value
currently in effect.
0
IPOLA
Current Polarity — This buffered bit selects the PMF Value register for the PWM0 and PWM1 pins in top/bottom
software correction in complementary mode.
0 PMF Value 0 register in next PWM cycle.
1 PMF Value 1 register in next PWM cycle.
Note: The IPOLx bits take effect at the beginning of the next load cycle, regardless of the state of the load okay
bit, LDOK. Select top/bottom software correction by writing 01 to the current select bits, ISENS[1:0], in the
PWM control register. Reading the IPOLx bits read the buffered value and not necessarily the value
currently in effect.
ISENS Correction Method
00 No correction
1
1
The current status pins can be used as general purpose input/output ports.
01 Manual correction
10 Current status sample correction on pins
IS0, IS1, and IS2 during deadtime
2
2
The polarity of the ISx pin is latched when both the top and bottom PWMs are off. At the 0%
and 100% duty cycle boundaries, there is no deadtime, so no new current value is sensed.
11 Current status sample on pins
IS0, IS1, and IS2
3
At the half cycle in center-aligned operation
At the end of the cycle in edge-aligned operation
3
Current is sensed even with 0% or 100% duty cycle.
Table 11-17. PMFCCTL Field Descriptions (continued)
Field Description