Datasheet

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
MC9S12E128 Data Sheet, Rev. 1.07
348 Freescale Semiconductor
11.3.2.24 PMF Deadtime A Register (PMFDTMA)
Read anytime. This register cannot be modified after the WP bit is set.
Module Base + 0x0026
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0 0 0 0
PMFDTMA
W
Reset 0 0 0 0 1 1 1 1 1 1111111
= Unimplemented or Reserved
Figure 11-30. PMF Deadtime A Register (PMFDTMA)
Table 11-31. PMFDTMA Field Descriptions
Field Description
11–0
PMFDTMA
PMF Deadtime A Bits — The 12-bit value written to this register is the number of PWM clock cycles in
complementary channel operation. A reset sets the PWM deadtime register to a default value of 0x0FFF,
selecting a deadtime of 256-PWM clock cycles minus one bus clock cycle.
Note: Deadtime is affected by changes to the prescaler value. The deadtime duration is determined as follows:
DT = P × PMFDTMA – 1, where DT is deadtime, P is the prescaler value, PMFDTMA is the programmed
value of dead time. For example: if the prescaler is programmed for a divide-by-two and the PMFDTMA is
set to five, then P = 2 and the deadtime value is equal to DT = 2 × 5 – 1 = 9 IPbus clock cycles. A special
case exists when the P = 1, then DT = PMFDTMA.