Datasheet

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 359
In an edge-aligned operation, the PWM counter is an up counter. The PWM output resolution is one bus
clock cycle.
PWM period = PWM modulus × PWM clock period
Figure 11-44. Edge-Aligned PWM Period
11.4.3.3 Duty Cycle
The signed 16-bit number written to the PMF value registers is the pulse width in PWM clock periods of
the PWM generator output.
NOTE
A PWM value less than or equal to zero deactivates the PWM output for the
entire PWM period. A PWM value greater than or equal to the modulus
activates the PWM output for the entire PWM period.
Table 11-46. PWM Value and Underflow Conditions
PMFVALx Condition PWM Value Used
$0000–$7FFF Normal Value in registers
$8000–$FFFF Underflow $0000
UP COUNTER
PWM CLOCK PERIOD
PWM PERIOD = 4 x PWM CLOCK PERIOD
MODULUS = 4
COUNT 1 2 3
4
Duty cycle
PMFVAL
MODULUS
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100×=