Datasheet

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
MC9S12E128 Data Sheet, Rev. 1.07
362 Freescale Semiconductor
In complementary channel operation, there are three additional features:
• Deadtime insertion
• Separate top and bottom pulse width correction for distortions are caused by deadtime inserted and
the motor drive characteristics
• Separate top and bottom output polarity control
• Swap functionality
11.4.5 Deadtime Generators
While in the complementary mode, each PWM pair can be used to drive top/bottom transistors, as shown
in Figure 11-49. Ideally, the PWM pairs are an inversion of each other. When the top PWM channel is
active, the bottom PWM channel is inactive, and vice versa.
NOTE
To avoid a short-circuit on the DC bus and endangering the transistor, there
must be no overlap of conducting intervals between top and bottom
transistor. But the transistor’s characteristics make its switching-off time
longer than switching-on time. To avoid the conducting overlap of top and
bottom transistors, deadtime needs to be inserted in the switching period.
Deadtime generators automatically insert software-selectable activation delays into each pair of PWM
outputs. The deadtime register (PMFDTMx) specifies the number of PWM clock cycles to use for
deadtime delay. Every time the deadtime generator inputs changes state, deadtime is inserted. Deadtime
forces both PWM outputs in the pair to the inactive state.
A method of correcting this, adding to or subtracting from the PWM value used, is discussed next.
Figure 11-49. Deadtime Generators
MUX
OUT0
OUTCTL0
MUX
OUT2
OUTCTL2
MUX
OUT4
OUTCTL4
PWM
GENERATOR
CURRENT
STATUS
DEADTIME
GENERATOR
OUT1
DEADTIME
GENERATOR
DEADTIME
GENERATOR
PWM0 &
PWM2 &
PWM4 &
OUT3
OUT5
TOP/BOTTOM
GENERATOR
TOP/BOTTOM
GENERATOR
TOP/BOTTOM
GENERATOR
TOP (PWM0)
TO FAULT
PROTECTION
TO FAULT
PROTECTION
TO FAULT
PROTECTION
BOTTOM (PWM1)
TOP (PWM2)
BOTTOM (PWM3)
TOP (PWM4)
BOTTOM (PWM5)
PWM1
PWM3
PWM5