Datasheet

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 367
Figure 11-55. Current-Status Sense Scheme for Deadtime Correction
If both D flip-flops latch low, DT0 = 0, DT1 = 0, during deadtime periods if current is large and flowing
out of the complementary circuit. See Figure 11-55. If both D flip-flops latch the high, DT0 = 1, DT1 = 1,
during deadtime periods if current is also large and flowing into the complementary circuit. However,
under low-current, the output voltage of the complementary circuit during deadtime is somewhere between
the high and low levels. The current cannot free-wheel throughout the opposition anti-body diode,
regardless of polarity, giving additional distortion when the current crosses zero. Sampled results will be
DT0 = 0 and DT1 = 1. Thus, the best time to change one PWM value register to another is just before the
current zero crossing.
Figure 11-56. Output Voltage Waveforms
PWM0
PWM1
DQ
CLK
DQ
CLK
VOLTAGE
SENSOR
IS0 PIN
PWM0
PWM1
DT0
DT1
POSITIVE
CURRENT
NEGATIVE
CURRENT
DEADTIME
PWM TO TOP
POSITIVE
NEGATIVE
PWM TO BOTTOM
LOAD VOLTAGE WITH
LOAD VOLTAGE WITH
TRANSISTOR
TRANSISTOR
HIGH POSITIVE CURRENT
LOW POSITIVE CURRENT
CURRENT
CURRENT
LOAD VOLTAGE WITH
HIGH NEGATIVE CURRENT
LOAD VOLTAGE WITH
NEGATIVE CURRENT
TBTB
T = DEADTIME INTERVAL BEFORE ASSERTION OF TOP PWM
B = DEADTIME INTERVAL BEFORE ASSERTION OF BOTTOM PWM
V
+