Datasheet

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)

MC9S12E128 Data Sheet, Rev. 1.07

378 Freescale Semiconductor

11.4.8.2 Automatic Fault Clearing

Setting a fault mode bit, FMODEx, conﬁgures faults from the FAULTx pin for automatic clearing.

When FMODEx is set, disabled PWM pins are enabled when the FAULTx pin returns to logic zero and a

new PWM half cycle begins. See Figure 11-76. Clearing the FFLAGx ﬂag does not affect disabled PWM

pins when FMODEx is set.

Figure 11-76. Automatic Fault Clearing

11.4.8.3 Manual Fault Clearing

Clearing a fault mode bit, FMODEx, conﬁgures faults from the FAULTx pin for manual clearing:

• PWM pins disabled by the FAULT0 pin or the FAULT2 pin are enabled by clearing the

corresponding FFLAGx flag. The time at which the PWM pins are enabled depends on the

corresponding QSMPx bit setting. If QSMPx = 00, the PWM pins are enabled on the next IP bus

cycle when the logic level detected by the filter at the fault pin is logic zero. If QSMPx = 01,10 or

11, the PWMs are enabled when the next PWM half cycle begins regardless of the state of the logic

level detected by the filter at the fault. See Figure 11-77 and Figure 11-78.

• PWM pins disabled by the FAULT1 pin or the FAULT3 pin are enabled when

— Software clears the corresponding FFLAGx ﬂag

— The ﬁlter detects a logic zero on the fault pin at the start of the next PWM half cycle boundary.

See Figure 11-79.

Figure 11-77. Manual Fault Clearing (Faults 0 & 2) — QSMP = 00

PWMS ENABLED PWMS DISABLED

PWMS ENABLED

FAULT PIN

DISABLED

ENABLED

PWMS ENABLED

FAULT0 OR

FAULT2

PWMS ENABLED

PWMS DISABLED

FFLAGx

CLEARED