Datasheet

Chapter 12 Pulse-Width Modulator (PWM8B6CV1)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 389
12.3.2.3 PWM Clock Select Register (PWMCLK)
Each PWM channel has a choice of two clocks to use as the clock source for that channel as described
below.
Read: anytime
Write: anytime
NOTE
Register bits PCLK0 to PCLK5 can be written anytime. If a clock select is
changed while a PWM signal is being generated, a truncated or stretched
pulse can occur during the transition.
2
PPOL2
Pulse Width Channel 2 Polarity
0 PWM channel 2 output is low at the beginning of the period, then goes high when the duty count is reached.
1 PWM channel 2 output is high at the beginning of the period, then goes low when the duty count is reached.
1
PPOL1
Pulse Width Channel 1 Polarity
0 PWM channel 1 output is low at the beginning of the period, then goes high when the duty count is reached.
1 PWM channel 1 output is high at the beginning of the period, then goes low when the duty count is reached.
0
PPOL0
Pulse Width Channel 0 Polarity
0 PWM channel 0 output is low at the beginning of the period, then goes high when the duty count is reached
1 PWM channel 0 output is high at the beginning of the period, then goes low when the duty count is reached.
76543210
R0 0
PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 12-5. PWM Clock Select Register (PWMCLK)
Table 12-4. PWMCLK Field Descriptions
Field Description
5
PCLK5
Pulse Width Channel 5 Clock Select
0 Clock A is the clock source for PWM channel 5.
1 Clock SA is the clock source for PWM channel 5.
4
PCLK4
Pulse Width Channel 4 Clock Select
0 Clock A is the clock source for PWM channel 4.
1 Clock SA is the clock source for PWM channel 4.
3
PCLK3
Pulse Width Channel 3 Clock Select
0 Clock B is the clock source for PWM channel 3.
1 Clock SB is the clock source for PWM channel 3.
Table 12-3. PWMPOL Field Descriptions (continued)
Field Description