Datasheet

Chapter 12 Pulse-Width Modulator (PWM8B6CV1)
MC9S12E128 Data Sheet, Rev. 1.07
390 Freescale Semiconductor
12.3.2.4 PWM Prescale Clock Select Register (PWMPRCLK)
This register selects the prescale clock source for clocks A and B independently.
Read: anytime
Write: anytime
NOTE
PCKB2–PCKB0 and PCKA2–PCKA0 register bits can be written anytime.
If the clock prescale is changed while a PWM signal is being generated, a
truncated or stretched pulse can occur during the transition.
2
PCLK2
Pulse Width Channel 2 Clock Select
0 Clock B is the clock source for PWM channel 2.
1 Clock SB is the clock source for PWM channel 2.
1
PCLK1
Pulse Width Channel 1 Clock Select
0 Clock A is the clock source for PWM channel 1.
1 Clock SA is the clock source for PWM channel 1.
0
PCLK0
Pulse Width Channel 0 Clock Select
0 Clock A is the clock source for PWM channel 0.
1 Clock SA is the clock source for PWM channel 0.
76543210
R0
PCKB2 PCKB1 PCKB0
0
PCKA2 PCKA1 PCKA0
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 12-6. PWM Prescaler Clock Select Register (PWMPRCLK)
Table 12-5. PWMPRCLK Field Descriptions
Field Description
6:5
PCKB[2:0]
Prescaler Select for Clock B — Clock B is 1 of two clock sources which can be used for channels 2 or 3. These
three bits determine the rate of clock B, as shown in Table 12-6.
2:0
PCKA[2:0]
Prescaler Select for Clock A — Clock A is 1 of two clock sources which can be used for channels 0, 1, 4, or 5.
These three bits determine the rate of clock A, as shown in Table 12-7.
Table 12-4. PWMCLK Field Descriptions (continued)
Field Description