Datasheet

Chapter 12 Pulse-Width Modulator (PWM8B6CV1)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 391
12.3.2.5 PWM Center Align Enable Register (PWMCAE)
The PWMCAE register contains six control bits for the selection of center aligned outputs or left aligned
outputs for each PWM channel. If the CAEx bit is set to a 1, the corresponding PWM output will be center
aligned. If the CAEx bit is cleared, the corresponding PWM output will be left aligned. Reference
Section 12.4.2.5, “Left Aligned Outputs, and Section 12.4.2.6, “Center Aligned Outputs, for a more
detailed description of the PWM output modes.
Read: anytime
Write: anytime
NOTE
Write these bits only when the corresponding channel is disabled.
Table 12-6. Clock B Prescaler Selects
PCKB2 PCKB1 PCKB0 Value of Clock B
0 0 0 Bus Clock
0 0 1 Bus Clock / 2
0 1 0 Bus Clock / 4
0 1 1 Bus Clock / 8
1 0 0 Bus Clock / 16
1 0 1 Bus Clock / 32
1 1 0 Bus Clock / 64
1 1 1 Bus Clock / 128
Table 12-7. Clock A Prescaler Selects
PCKA2 PCKA1 PCKA0 Value of Clock A
0 0 0 Bus Clock
0 0 1 Bus Clock / 2
0 1 0 Bus Clock / 4
0 1 1 Bus Clock / 8
1 0 0 Bus Clock / 16
1 0 1 Bus Clock / 32
1 1 0 Bus Clock / 64
1 1 1 Bus Clock / 128
76543210
R0 0
CAE5 CAE4 CAE3 CAE2 CAE1 CAE0
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 12-7. PWM Center Align Enable Register (PWMCAE)