Datasheet

Chapter 12 Pulse-Width Modulator (PWM8B6CV1)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 399
To calculate the output period, take the selected clock source period for the channel of interest (A, B, SA,
or SB) and multiply it by the value in the period register for that channel:
• Left aligned output (CAEx = 0)
• PWMx period = channel clock period * PWMPERx center aligned output (CAEx = 1)
• PWMx period = channel clock period * (2 * PWMPERx)
For boundary case programming values, please refer to Section 12.4.2.8, “PWM Boundary Cases.”
76543210
R
Bit 7 6 5 4321Bit 0
W
Reset 0 0 0 00000
Figure 12-21. PWM Channel Period Registers (PWMPER0)
76543210
R
Bit 7 6 5 4321Bit 0
W
Reset 0 0 0 00000
Figure 12-22. PWM Channel Period Registers (PWMPER1)
76543210
R
Bit 7 6 5 4321Bit 0
W
Reset 0 0 0 00000
Figure 12-23. PWM Channel Period Registers (PWMPER2)
76543210
R
Bit 7 6 5 4321Bit 0
W
Reset 0 0 0 00000
Figure 12-24. PWM Channel Period Registers (PWMPER3)
76543210
R
Bit 7 6 5 4321Bit 0
W
Reset 0 0 0 00000
Figure 12-25. PWM Channel Period Registers (PWMPER4)