Datasheet

Chapter 12 Pulse-Width Modulator (PWM8B6CV1)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 413
Table 12-12 is used to summarize which channels are used to set the various control bits when in 16-bit
mode.
12.4.2.8 PWM Boundary Cases
Table 12-13 summarizes the boundary conditions for the PWM regardless of the output mode (left aligned
or center aligned) and 8-bit (normal) or 16-bit (concatenation):
12.5 Resets
The reset state of each individual bit is listed within the register description section (see Section 12.3,
“Memory Map and Register Definition,” which details the registers and their bit-fields. All special
functions or modes which are initialized during or just following reset are described within this section.
• The 8-bit up/down counter is configured as an up counter out of reset.
• All the channels are disabled and all the counters don’t count.
12.6 Interrupts
The PWM8B6CV1 module has only one interrupt which is generated at the time of emergency shutdown,
if the corresponding enable bit (PWMIE) is set. This bit is the enable for the interrupt. The interrupt flag
PWMIF is set whenever the input level of the PWM5 channel changes while PWM5ENA=1 or when
PWMENA is being asserted while the level at PWM5 is active.
A description of the registers involved and affected due to this interrupt is explained in Section 12.3.2.15,
“PWM Shutdown Register (PWMSDN).”
Table 12-12. 16-bit Concatenation Mode Summary
CONxx PWMEx PPOLx PCLKx CAEx PWMx Output
CON45 PWME5 PPOL5 PCLK5 CAE5 PWM5
CON23 PWME3 PPOL3 PCLK3 CAE3 PWM3
CON01 PWME1 PPOL1 PCLK1 CAE1 PWM1
Table 12-13. PWM Boundary Cases
PWMDTYx PWMPERx PPOLx PWMx Output
0x0000
(indicates no duty)
>0x0000 1 Always Low
0x0000
(indicates no duty)
>0x0000 0 Always High
XX 0x0000
1
(indicates no period)
1
Counter = 0x0000 and does not count.
1 Always High
XX 0x0000
1
(indicates no period)
0 Always Low
>= PWMPERx XX 1 Always High
>= PWMPERx XX 0 Always Low