Datasheet

Chapter 13 Timer Module (TIM16B4CV1)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 423
13.3.2.3 Output Compare 7 Mask Register (OC7M)
Read: Anytime
Write: Anytime
13.3.2.4 Output Compare 7 Data Register (OC7D)
Read: Anytime
Write: Anytime
13.3.2.5 Timer Count Register (TCNT)
76543210
R
OC7M7 OC7M6 OC7M5 OC7M4
0000
W
Reset 0 0 0 00000
Figure 13-8. Output Compare 7 Mask Register (OC7M)
Table 13-4. OC7M Field Descriptions
Field Description
7:4
OC7M[7:4]
Output Compare 7 Mask — Setting the OC7Mx (x ranges from 4 to 6) will set the corresponding port to be an
output port when the corresponding TIOSx (x ranges from 4 to 6) bit is set to be an output compare.
Note: A successful channel 7 output compare overrides any channel 6:4 compares. For each OC7M bit that is
set, the output compare action reflects the corresponding OC7D bit.
76543210
R
OC7D7 OC7D6 OC7D5 OC7D4
0000
W
Reset 0 0 0 00000
Figure 13-9. Output Compare 7 Data Register (OC7D)
Table 13-5. OC7D Field Descriptions
Field Description
7:4
OC7D[7:4]
Output Compare 7 Data — A channel 7 output compare can cause bits in the output compare 7 data register
to transfer to the timer port data register depending on the output compare 7 mask register.
15 14 13 12 11 10 9 9
R
TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8
W
Reset 0 0 0 00000
Figure 13-10. Timer Count Register High (TCNTH)