Datasheet

Chapter 13 Timer Module (TIM16B4CV1)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 425
13.3.2.7 Timer Toggle On Overflow Register 1 (TTOV)
Read: Anytime
Write: Anytime
13.3.2.8 Timer Control Register 1 (TCTL1)
Read: Anytime
Write: Anytime
5
TSFRZ
Timer Stops While in Freeze Mode
0 Allows the timer counter to continue running while in freeze mode.
1 Disables the timer counter whenever the MCU is in freeze mode. This is useful for emulation.
TSFRZ does not stop the pulse accumulator.
4
TFFCA
Timer Fast Flag Clear All
0 Allows the timer flag clearing to function normally.
1 For TFLG1(0x000E), a read from an input capture or a write to the output compare channel (0x0010–0x001F)
causes the corresponding channel flag, CnF, to be cleared. For TFLG2 (0x000F), any access to the TCNT
register (0x0004, 0x0005) clears the TOF flag. Any access to the PACNT registers (0x0022, 0x0023) clears
the PAOVF and PAIF flags in the PAFLG register (0x0021). This has the advantage of eliminating software
overhead in a separate clear sequence. Extra care is required to avoid accidental flag clearing due to
unintended accesses.
76543210
R
TOV7 TOV6 TOV5 TOV4
0000
W
Reset 0 0 0 00000
Figure 13-13. Timer Toggle On Overflow Register 1 (TTOV)
Table 13-7. TTOV Field Descriptions
Field Description
7:4
TOV[7:4]
Toggle On Overflow Bits — TOVx toggles output compare pin on overflow. This feature only takes effect when
in output compare mode. When set, it takes precedence over forced output compare but not channel 7 override
events.
0 Toggle output compare pin on overflow feature disabled.
1 Toggle output compare pin on overflow feature enabled.
76543210
R
OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4
W
Reset 0 0 0 00000
Figure 13-14. Timer Control Register 1 (TCTL1)
Table 13-6. TSCR1 Field Descriptions (continued)
Field Description