Datasheet

Chapter 13 Timer Module (TIM16B4CV1)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 427
13.3.2.9 Timer Control Register 3 (TCTL3)
Read: Anytime
Write: Anytime.
76543210
R
EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A
W
Reset 0 0 0 00000
Figure 13-15. Timer Control Register 3 (TCTL3)
Table 13-10. TCTL3/TCTL4 Field Descriptions
Field Description
7:0
EDGnB
EDGnA
Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector
circuits.
Table 13-11. Edge Detector Circuit Configuration
EDGnB EDGnA Configuration
0 0 Capture disabled
0 1 Capture on rising edges only
1 0 Capture on falling edges only
1 1 Capture on any edge (rising or falling)