Datasheet

Chapter 13 Timer Module (TIM16B4CV1)
MC9S12E128 Data Sheet, Rev. 1.07
428 Freescale Semiconductor
13.3.2.10 Timer Interrupt Enable Register (TIE)
Read: Anytime
Write: Anytime.
13.3.2.11 Timer System Control Register 2 (TSCR2)
Read: Anytime
Write: Anytime.
76543210
R
C7I C6I C5I C4I
0000
W
Reset 0 0 0 00000
Figure 13-16. Timer Interrupt Enable Register (TIE)
Table 13-12. TIE Field Descriptions
Field Description
7:4
C7I:C0I
Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in
the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set,
the corresponding flag is enabled to cause a interrupt.
76543210
R
TOI
000
TCRE PR2 PR1 PR0
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 13-17. Timer System Control Register 2 (TSCR2)
Table 13-13. TSCR2 Field Descriptions
Field Description
7
TOI
Timer Overflow Interrupt Enable
0 Interrupt inhibited.
1 Hardware interrupt requested when TOF flag set.
3
TCRE
Timer Counter Reset Enable — This bit allows the timer counter to be reset by a successful output compare 7
event. This mode of operation is similar to an up-counting modulus counter.
0 Counter reset inhibited and counter free runs.
1 Counter reset by a successful output compare 7.
If TC7 = 0x0000 and TCRE = 1, TCNT will stay at 0x0000 continuously. If TC7 = 0xFFFF and TCRE = 1, TOF
will never be set when TCNT is reset from 0xFFFF to 0x0000.
2
PR[2:0]
Timer Prescaler Select — These three bits select the frequency of the timer prescaler clock derived from the
Bus Clock as shown in Table 13-14.