Datasheet

Chapter 13 Timer Module (TIM16B4CV1)

MC9S12E128 Data Sheet, Rev. 1.07

Freescale Semiconductor 429

NOTE

The newly selected prescale factor will not take effect until the next

synchronized edge where all prescale counter stages equal zero.

13.3.2.12 Main Timer Interrupt Flag 1 (TFLG1)

Read: Anytime

Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero

will not affect current status of the bit.

Table 13-14. Timer Clock Selection

PR2 PR1 PR0 Timer Clock

0 0 0 Bus Clock / 1

0 0 1 Bus Clock / 2

0 1 0 Bus Clock / 4

0 1 1 Bus Clock / 8

1 0 0 Bus Clock / 16

1 0 1 Bus Clock / 32

1 1 0 Bus Clock / 64

1 1 1 Bus Clock / 128

76543210

C7F C6F C5F C4F

0000

Reset 0 0 0 00000

Figure 13-18. Main Timer Interrupt Flag 1 (TFLG1)

Table 13-15. TRLG1 Field Descriptions

Field Description

7:4

C[7:4]F

Input Capture/Output Compare Channel “x” Flag — These flags are set when an input capture or output

compare event occurs. Clear a channel ﬂag by writing one to it.

When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare channel

(0x0010–0x001F) will cause the corresponding channel ﬂag CxF to be cleared.