Datasheet

Chapter 14 Dual Output Voltage Regulator (VREG3V3V2)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 441
14.2 External Signal Description
Due to the nature of VREG3V3V2 being a voltage regulator providing the chip internal power supply
voltages most signals are power supply signals connected to pads.
Table 14-1 shows all signals of VREG3V3V2 associated with pins.
NOTE
Check device overview chapter for connectivity of the signals.
14.2.1 V
DDR
— Regulator Power Input
Signal V
DDR
is the power input of VREG3V3V2. All currents sourced into the regulator loads flow
through this pin. A chip external decoupling capacitor (100 nF...220 nF, X7R ceramic) between V
DDR
and
V
SSR
can smoothen ripple on V
DDR
.
For entering shutdown mode, pin V
DDR
should also be tied to ground on devices without a V
REGEN
pin.
14.2.2 V
DDA
, V
SSA
— Regulator Reference Supply
Signals V
DDA
/V
SSA
which are supposed to be relatively quiet are used to supply the analog parts of the
regulator. Internal precision reference circuits are supplied from these signals. A chip external decoupling
capacitor (100 nF...220 nF, X7R ceramic) between V
DDA
and V
SSA
can further improve the quality of this
supply.
Table 14-1. VREG3V3V2 — Signal Properties
Name Port Function Reset State Pull Up
V
DDR
— VREG3V3V2 power input (positive supply) — —
V
DDA
— VREG3V3V2 quiet input (positive supply) — —
V
SSA
— VREG3V3V2 quiet input (ground) — —
V
DD
— VREG3V3V2 primary output (positive supply) — —
V
SS
— VREG3V3V2 primary output (ground) — —
V
DDPLL
— VREG3V3V2 secondary output (positive supply) — —
V
SSPLL
— VREG3V3V2 secondary output (ground) — —
V
REGEN
(optional) — VREG3V3V2 (Optional) Regulator Enable — —