Datasheet

Chapter 14 Dual Output Voltage Regulator (VREG3V3V2)
MC9S12E128 Data Sheet, Rev. 1.07
444 Freescale Semiconductor
The regulator is a linear series regulator with a bandgap reference in its full-performance mode and a
voltage clamp in reduced-power mode. All load currents flow from input V
DDR
to V
SS
or V
SSPLL
, the
reference circuits are connected to V
DDA
and V
SSA
.
14.4.2 Full-Performance Mode
In full-performance mode, a fraction of the output voltage (V
DD
) and the bandgap reference voltage are
fed to an operational amplifier. The amplified input voltage difference controls the gate of an output driver
which basically is a large NMOS transistor connected to the output.
14.4.3 Reduced-Power Mode
In reduced-power mode, the driver gate is connected to a buffered fraction of the input voltage (V
DDR
).
The operational amplifier and the bandgap are disabled to reduce power consumption.
14.4.4 LVD — Low-Voltage Detect
sub-block LVD is responsible for generating the low-voltage interrupt (LVI). LVD monitors the input
voltage (V
DDA
–V
SSA
) and continuously updates the status flag LVDS. Interrupt flag LVIF is set whenever
status flag LVDS changes its value. The LVD is available in FPM and is inactive in reduced-power mode
and shutdown mode.
14.4.5 POR — Power-On Reset
This functional block monitors output V
DD
. If V
DD
is below V
PORD
, signal POR is high, if it exceeds
V
PORD
, the signal goes low. The transition to low forces the CPU in the power-on sequence.
Due to its role during chip power-up this module must be active in all operating modes of VREG3V3V2.
14.4.6 LVR — Low-Voltage Reset
Block LVR monitors the primary output voltage V
DD
. If it drops below the assertion level (V
LVRA
) signal
LVR asserts and when rising above the deassertion level (V
LVRD
) signal LVR negates again. The LVR
function is available only in full-performance mode.
14.4.7 CTRL — Regulator Control
This part contains the register block of VREG3V3V2 and further digital functionality needed to control
the operating modes. CTRL also represents the interface to the digital core logic.