Datasheet

Chapter 15 Background Debug Module (BDMV4)

MC9S12E128 Data Sheet, Rev. 1.07

448 Freescale Semiconductor

• Nine hardware commands using free cycles, if available, for minimal CPU intervention

• Hardware commands not requiring active BDM

• 15 ﬁrmware commands execute from the standard BDM ﬁrmware lookup table

• Instruction tagging capability

• Software control of BDM operation during wait mode

• Software selectable clocks

• When secured, hardware commands are allowed to access the register space in special single-chip

mode, if the FLASH and EEPROM erase tests fail.

15.1.2 Modes of Operation

BDM is available in all operating modes but must be enabled before ﬁrmware commands are executed.

Some system peripherals may have a control bit which allows suspending the peripheral function during

background debug mode.

15.1.2.1 Regular Run Modes

All of these operations refer to the part in run mode. The BDM does not provide controls to conserve power

during run mode.

• Normal operation

General operation of the BDM is available and operates the same in all normal modes.

• Special single-chip mode

In special single-chip mode, background operation is enabled and active out of reset. This allows

programming a system with blank memory.

• Special peripheral mode

BDM is enabled and active immediately out of reset. BDM can be disabled

by clearing the BDMACT bit in the BDM status (BDMSTS) register. The

BDM serial system should not be used in special peripheral mode.

• Emulation modes

General operation of the BDM is available and operates the same as in normal modes.

15.1.2.2 Secure Mode Operation

If the part is in secure mode, the operation of the BDM is reduced to a small subset of its regular run mode

operation. Secure operation prevents access to FLASH or EEPROM other than allowing erasure.

15.2 External Signal Description

A single-wire interface pin is used to communicate with the BDM system. Two additional pins are used

for instruction tagging. These pins are part of the multiplexed external bus interface (MEBI) sub-block and

all interfacing between the MEBI and BDM is done within the core interface boundary. Functional

descriptions of the pins are provided below for completeness.