Datasheet

Chapter 15 Background Debug Module (BDMV4)
MC9S12E128 Data Sheet, Rev. 1.07
450 Freescale Semiconductor
15.3 Memory Map and Register Definition
A summary of the registers associated with the BDM is shown in Figure 15-2. Registers are accessed by
host-driven communications to the BDM hardware using READ_BD and WRITE_BD commands.
Detailed descriptions of the registers and associated bits are given in the subsections that follow.
15.3.1 Module Memory Map
Table 15-1. INT Memory Map
Register
Address
Use Access
Reserved —
BDM Status Register (BDMSTS) R/W
Reserved —
BDM CCR Holding Register (BDMCCR) R/W
7 BDM Internal Register Position (BDMINR) R
8– Reserved —