Chapter 15 Background Debug Module (BDMV4)
MC9S12E128 Data Sheet, Rev. 1.07
454 Freescale Semiconductor
1 0 Alternate clock (refer to the device overview chapter to determine the alternate clock
source)
1 1 Bus clock dependent on the PLL
Table 15-3. BDM Clock Sources
PLLSEL CLKSW BDMCLK
