Datasheet

MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 473
Chapter 16
Debug Module (DBGV1)
16.1 Introduction
This section describes the functionality of the debug (DBG) sub-block of the HCS12 core platform.
The DBG module is designed to be fully compatible with the existing BKP_HCS12_A module (BKP
mode) and furthermore provides an on-chip trace buffer with flexible triggering capability (DBG mode).
The DBG module provides for non-intrusive debug of application software. The DBG module is optimized
for the HCS12 16-bit architecture.
16.1.1 Features
The DBG module in BKP mode includes these distinctive features:
• Full or dual breakpoint mode
— Compare on address and data (full)
— Compare on either of two addresses (dual)
• BDM or SWI breakpoint
— Enter BDM on breakpoint (BDM)
— Execute SWI on breakpoint (SWI)
• Tagged or forced breakpoint
— Break just before a specific instruction will begin execution (TAG)
— Break on the first instruction boundary after a match occurs (Force)
• Single, range, or page address compares
— Compare on address (single)
— Compare on address 256 byte (range)
— Compare on any 16K page (page)
• At forced breakpoints compare address on read or write
• High and/or low byte data compares
• Comparator C can provide an additional tag or force breakpoint (enhancement for BKP mode)