Datasheet

Chapter 16 Debug Module (DBGV1)
MC9S12E128 Data Sheet, Rev. 1.07
474 Freescale Semiconductor
The DBG in DBG mode includes these distinctive features:
• Three comparators (A, B, and C)
— Dual mode, comparators A and B used to compare addresses
— Full mode, comparator A compares address and comparator B compares data
— Can be used as trigger and/or breakpoint
— Comparator C used in LOOP1 capture mode or as additional breakpoint
• Four capture modes
— Normal mode, change-of-flow information is captured based on trigger specification
— Loop1 mode, comparator C is dynamically updated to prevent redundant change-of-flow
storage.
— Detail mode, address and data for all cycles except program fetch (P) and free (f) cycles are
stored in trace buffer
— Profile mode, last instruction address executed by CPU is returned when trace buffer address is
read
• Two types of breakpoint or debug triggers
— Break just before a specific instruction will begin execution (tag)
— Break on the first instruction boundary after a match occurs (force)
• BDM or SWI breakpoint
— Enter BDM on breakpoint (BDM)
— Execute SWI on breakpoint (SWI)
• Nine trigger modes for comparators A and B
—A
— A or B
— A then B
— A and B, where B is data (full mode)
— A and not B, where B is data (full mode)
— Event only B, store data
— A then event only B, store data
— Inside range, A ≤ address ≤ B
— Outside range, address < Α or address > B
• Comparator C provides an additional tag or force breakpoint when capture mode is not configured
in LOOP1 mode.
• Sixty-four word (16 bits wide) trace buffer for storing change-of-flow information, event only data
and other bus information.
— Source address of taken conditional branches (long, short, bit-conditional, and loop constructs)
— Destination address of indexed JMP, JSR, and CALL instruction.
— Destination address of RTI, RTS, and RTC instructions
— Vector address of interrupts, except for SWI and BDM vectors