Datasheet

Chapter 16 Debug Module (DBGV1)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 477
Figure 16-2. DBG Block Diagram in DBG Mode
16.2 External Signal Description
The DBG sub-module relies on the external bus interface (generally the MEBI) when the DBG is matching
on the external bus.
The tag pins in Table 16-1 (part of the MEBI) may also be a part of the breakpoint operation.
Table 16-1. External System Pins Associated with DBG and MEBI
Pin Name Pin Functions Description
BKGD/MODC/
TAGHI
TAGHI When instruction tagging is on, a 0 at the falling edge of E tags the high half of the
instruction word being read into the instruction queue.
PE3/
LSTRB/ TAGLO TAGLO In expanded wide mode or emulation narrow modes, when instruction tagging is on
and low strobe is enabled, a 0 at the falling edge of E tags the low half of the
instruction word being read into the instruction queue.
TAG
FORCE
ADDRESS BUS
MATCH_A
CONTROL
READ DATA BUS
READ/WRITE
STORE
MCU IN BDM
M
U
X
POINTER
REGISTER
MATCH_B
M
U
X
EVENT ONLY
WRITE DATA BUS
TRACE BUFFER
DBG READ DATA BUS
DBG MODE ENABLE
M
U
X
WRITE DATA BUS
READ DATA BUS
READ/WRITE
MATCH_C
LOOP1
DETAIL
M
U
X
PROFILE CAPTURE MODE
CPU PROGRAM COUNTER
CONTROL
COMPARATOR A
ADDRESS/DATA/CONTROL
COMPARATOR B
COMPARATOR C
REGISTERS
TRACER
BUFFER
CONTROL
LOGIC
CHANGE-OF-FLOW
INDICATORS
OR PROFILING DATA
64 x 16 BIT
WORD
TRACE
BUFFER
PROFILE
CAPTURE
REGISTER
LAST
INSTRUCTION
ADDRESS
BUS CLOCK
INSTRUCTION
LAST CYCLE