Datasheet

Chapter 16 Debug Module (DBGV1)
MC9S12E128 Data Sheet, Rev. 1.07
480 Freescale Semiconductor
16.3.2.1 Debug Control Register 1 (DBGC1)
NOTE
All bits are used in DBG mode only.
NOTE
This register cannot be written if BKP mode is enabled (BKABEN in
DBGC2 is set).
76543210
R
DBGEN ARM TRGSEL BEGIN DBGBRK
0
CAPMOD
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 16-4. Debug Control Register (DBGC1)
Table 16-3. DBGC1 Field Descriptions
Field Description
7
DBGEN
DBG Mode Enable Bit — The DBGEN bit enables the DBG module for use in DBG mode. This bit cannot be
set if the MCU is in secure mode.
0 DBG mode disabled
1 DBG mode enabled
6
ARM
Arm Bit — The ARM bit controls whether the debugger is comparing and storing data in the trace buffer. See
Section 16.4.2.4, “Arming the DBG Module,” for more information.
0 Debugger unarmed
1 Debugger armed
Note: This bit cannot be set if the DBGEN bit is not also being set at the same time. For example, a write of 01
to DBGEN[7:6] will be interpreted as a write of 00.
5
TRGSEL
Trigger Selection Bit — The TRGSEL bit controls the triggering condition for comparators A and B in DBG
mode. It serves essentially the same function as the TAGAB bit in the DBGC2 register does in BKP mode. See
Section 16.4.2.1.2, “Trigger Selection,” for more information. TRGSEL may also determine the type of breakpoint
based on comparator A and B if enabled in DBG mode (DBGBRK = 1). Please refer to Section 16.4.3.1,
“Breakpoint Based on Comparator A and B.”
0 Trigger on any compare address match
1 Trigger before opcode at compare address gets executed (tagged-type)
4
BEGIN
Begin/End Trigger Bit — The BEGIN bit controls whether the trigger begins or ends storing of data in the trace
buffer. See Section 16.4.2.8.1, “Storing with Begin-Trigger,” and Section 16.4.2.8.2, “Storing with End-Trigger,”
for more details.
0 Trigger at end of stored data
1 Trigger before storing data