Datasheet

Chapter 16 Debug Module (DBGV1)
MC9S12E128 Data Sheet, Rev. 1.07
482 Freescale Semiconductor
16.3.2.2 Debug Status and Control Register (DBGSC)
76543210
RAF BF CF 0
TRG
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 16-5. Debug Status and Control Register (DBGSC)
Table 16-5. DBGSC Field Descriptions
Field Description
7
AF
Trigger A Match Flag — The AF bit indicates if trigger A match condition was met since arming. This bit is
cleared when ARM in DBGC1 is written to a 1 or on any write to this register.
0 Trigger A did not match
1 Trigger A match
6
BF
Trigger B Match Flag — The BF bit indicates if trigger B match condition was met since arming.This bit is
cleared when ARM in DBGC1 is written to a 1 or on any write to this register.
0 Trigger B did not match
1 Trigger B match
5
CF
Comparator C Match Flag — The CF bit indicates if comparator C match condition was met since arming.This
bit is cleared when ARM in DBGC1 is written to a 1 or on any write to this register.
0 Comparator C did not match
1 Comparator C match
3:0
TRG
Trigger Mode Bits — The TRG bits select the trigger mode of the DBG module as shown Table 16-6. See
Section 16.4.2.5, “Trigger Modes,” for more detail.
Table 16-6. Trigger Mode Encoding
TRG Value Meaning
0000 A only
0001 A or B
0010 A then B
0011 Event only B
0100 A then event only B
0101 A and B (full mode)
0110 A and Not B (full mode)
0111 Inside range
1000 Outside range
1001
↓
1111
Reserved
(Defaults to A only)