Datasheet

Chapter 16 Debug Module (DBGV1)
MC9S12E128 Data Sheet, Rev. 1.07
486 Freescale Semiconductor
16.3.2.6 Debug Comparator C Register (DBGCC)
DBGCXX DBGCXH[15:12]
PAGSEL EXTCMP
BIT 15 BIT 14 BIT 13 BIT 12
76
0
5
0
4
3 2 1 BIT 0
SEE NOTE 1
PORTK/XAB
XAB21 XAB20 XAB19 XAB18 XAB17 XAB16 XAB15 XAB14
PPAGE
PIX7 PIX6 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0
SEE NOTE 2
NOTES:
1. In BKP and DBG mode, PAGSEL selects the type of paging as shown in Table 16-11.
2. Current HCS12 implementations are limited to six PPAGE bits, PIX[5:0]. Therefore, EXTCMP[5:4] = 00.
Figure 16-10. Comparator C Extended Comparison in BKP/DBG Mode
15 14 13 12 11 10 9 8
R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 16-11. Debug Comparator C Register High (DBGCCH)
76543210
R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 16-12. Debug Comparator C Register Low (DBGCCL)
Table 16-12. DBGCC Field Descriptions
Field Description
15:0 Comparator C Compare Bits — The comparator C compare bits control whether comparator C will compare
the address bus bits [15:0] to a logic 1 or logic 0. See Table 16-13.
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
Note: This register will be cleared automatically when the DBG module is armed in LOOP1 mode.
BKP/DBG MODE