Datasheet

Chapter 16 Debug Module (DBGV1)
MC9S12E128 Data Sheet, Rev. 1.07
492 Freescale Semiconductor
16.3.2.10 Debug Comparator A Register (DBGCA)
16.3.2.11 Debug Comparator B Extended Register (DBGCBX)
15 14 13 12 11 10 9 8
R
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
Reset 0 0 0 00000
Figure 16-17. Debug Comparator A Register High (DBGCAH)
76543210
R
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
Reset 0 0 0 00000
Figure 16-18. Debug Comparator A Register Low (DBGCAL)
Table 16-21. DBGCA Field Descriptions
Field Description
15:0
15:0
Comparator A Compare Bits — The comparator A compare bits control whether comparator A compares the
address bus bits [15:0] to a logic 1 or logic 0. See Table 16-20.
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
76543210
R
PAGSEL EXTCMP
W
Reset 0 0 0 00000
Figure 16-19. Debug Comparator B Extended Register (DBGCBX)
Table 16-22. DBGCBX Field Descriptions
Field Description
7:6
PAGSEL
Page Selector Field — If DBGEN is set in DBGC1, then PAGSEL selects the type of paging as shown in
Table 16-11.
DPAGE and EPAGE are not yet implemented so the value in bit 7 will be ignored (i.e., PAGSEL values of 10 and
11 will be interpreted as values of 00 and 01, respectively.)
In BKP mode, PAGSEL has no meaning and EXTCMP[5:0] are compared to address bits [19:14] if the address
is in the FLASH/ROM memory space.
5:0
EXTCMP
Comparator B Extended Compare Bits — The EXTCMP bits are used as comparison address bits as shown
in Table 16-11 along with the appropriate PPAGE, DPAGE, or EPAGE signal from the core. Also see Table 16-20.