Datasheet
Chapter 17 Interrupt (INTV1)
MC9S12E128 Data Sheet, Rev. 1.07
506 Freescale Semiconductor
The interrupt sub-block decodes the priority of all system exception requests and provides the applicable
vector for processing the exception. The INT supports I-bit maskable and X-bit maskable interrupts, a
non-maskable unimplemented opcode trap, a non-maskable software interrupt (SWI) or background debug
mode request, and three system reset vector requests. All interrupt related exception requests are managed
by the interrupt sub-block (INT).
17.1.1 Features
The INT includes these features:
• Provides two to 122 I-bit maskable interrupt vectors (0xFF00–0xFFF2)
• Provides one X-bit maskable interrupt vector (0xFFF4)
• Provides a non-maskable software interrupt (SWI) or background debug mode request vector
(0xFFF6)
• Provides a non-maskable unimplemented opcode trap (TRAP) vector (0xFFF8)
• Provides three system reset vectors (0xFFFA–0xFFFE) (reset, CMR, and COP)
• Determines the appropriate vector and drives it onto the address bus at the appropriate time
• Signals the CPU that interrupts are pending
• Provides control registers which allow testing of interrupts
• Provides additional input signals which prevents requests for servicing I and X interrupts
• Wakes the system from stop or wait mode when an appropriate interrupt occurs or whenever
XIRQ
is active, even if
XIRQ is masked
• Provides asynchronous path for all I and X interrupts, (0xFF00–0xFFF4)
• (Optional) selects and stores the highest priority I interrupt based on the value written into the
HPRIO register
17.1.2 Modes of Operation
The functionality of the INT sub-block in various modes of operation is discussed in the subsections that
follow.
• Normal operation
The INT operates the same in all normal modes of operation.
• Special operation
Interrupts may be tested in special modes through the use of the interrupt test registers.
• Emulation modes
The INT operates the same in emulation modes as in normal modes.
• Low power modes
See Section 17.4.1, “Low-Power Modes,” for details