Datasheet

Chapter 17 Interrupt (INTV1)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 507
17.2 External Signal Description
Most interfacing with the interrupt sub-block is done within the core. However, the interrupt does receive
direct input from the multiplexed external bus interface (MEBI) sub-block of the core for the
IRQ and
XIRQ pin data.
17.3 Memory Map and Register Definition
Detailed descriptions of the registers and associated bits are given in the subsections that follow.
17.3.1 Module Memory Map
17.3.2 Register Descriptions
17.3.2.1 Interrupt Test Control Register
Read: See individual bit descriptions
Write: See individual bit descriptions
Table 17-1. INT Memory Map
Address
Offset
Use Access
0x0015 Interrupt Test Control Register (ITCR) R/W
0x0016 Interrupt Test Registers (ITEST) R/W
0x001F Highest Priority Interrupt (Optional) (HPRIO) R/W
76543210
R000
WRTINT ADR3 ADR2 ADR1 ADR0
W
Reset 0 0 0 01111
= Unimplemented or Reserved
Figure 17-2. Interrupt Test Control Register (ITCR)