Datasheet

Chapter 17 Interrupt (INTV1)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 509
17.3.2.3 Highest Priority I Interrupt (Optional)
Read: Anytime
Write: Only if I mask in CCR = 1
17.4 Functional Description
The interrupt sub-block processes all exception requests made by the CPU. These exceptions include
interrupt vector requests and reset vector requests. Each of these exception types and their overall priority
level is discussed in the subsections below.
17.4.1 Low-Power Modes
The INT does not contain any user-controlled options for reducing power consumption. The operation of
the INT in low-power modes is discussed in the following subsections.
17.4.1.1 Operation in Run Mode
The INT does not contain any options for reducing power in run mode.
17.4.1.2 Operation in Wait Mode
Clocks to the INT can be shut off during system wait mode and the asynchronous interrupt path will be
used to generate the wake-up signal upon recognition of a valid interrupt or any
XIRQ request.
17.4.1.3 Operation in Stop Mode
Clocks to the INT can be shut off during system stop mode and the asynchronous interrupt path will be
used to generate the wake-up signal upon recognition of a valid interrupt or any
XIRQ request.
76543210
R
PSEL7 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1
0
W
Reset 1 1 1 10010
= Unimplemented or Reserved
Figure 17-4. Highest Priority I Interrupt Register (HPRIO)
Table 17-4. HPRIO Field Descriptions
Field Description
7:1
PSEL[7:1]
Highest Priority I Interrupt Select Bits — The state of these bits determines which I-bit maskable interrupt will
be promoted to highest priority (of the I-bit maskable interrupts). To promote an interrupt, the user writes the least
significant byte of the associated interrupt vector address to this register. If an unimplemented vector address or
a non I-bit masked vector address (value higher than 0x00F2) is written, IRQ (0xFFF2) will be the default highest
priority interrupt.