Datasheet

Chapter 17 Interrupt (INTV1)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 511
17.7 Exception Priority
The priority (from highest to lowest) and address of all exception vectors issued by the INT upon request
by the CPU is shown in Table 17-5.
Table 17-5. Exception Vector Map and Priority
Vector Address Source
0xFFFE–0xFFFF System reset
0xFFFC–0xFFFD Crystal monitor reset
0xFFFA–0xFFFB COP reset
0xFFF8–0xFFF9 Unimplemented opcode trap
0xFFF6–0xFFF7 Software interrupt instruction (SWI) or BDM vector request
0xFFF4–0xFFF5
XIRQ signal
0xFFF2–0xFFF3
IRQ signal
0xFFF0–0xFF00 Device-specific I-bit maskable interrupt sources (priority in descending order)